The present invention relates to field effect transistors (FETs) and, in particular, to trench metal-oxide-semiconductor (MOS) transistors and methods of fabricating the same.
Power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are well known in the semiconductor industry. One type of MOSFET is a double-diffused trench MOSFET, or what is known as a “trench DMOS” transistor. A cross-sectional view of a portion of a typical n-channel trench DMOS transistor 10 is shown in FIG. 1. It should be pointed out that the relative thickness of the various layers is not necessarily drawn to scale.
The trench DMOS transistor 10, shown in FIG. 1, includes an n-type substrate 100. An n-type epitaxial layer 102 is formed over substrate 100, and a p-type body region 108 is formed in epitaxial layer 102 through an implant/diffusion process. One or more trenches 109 extend through body region 108 and into region 102a of epitaxial layer 102. Gate oxide layer 104 lines the sidewalls and bottom of each trench 109 and a conductive material 106, typically doped polysilicon, lines gate oxide layer 104 and fills each trench 109. N+ source regions 110 flank each trench 109 and extend a predetermined distance into body region 108. Heavy body regions 112 are positioned within body region 108, between source regions 110, and extend a predetermined distance into body region 108. During the high temperature cycles of the process (e.g., the anneal steps for activating the dopants in body region 108, source regions 110, and heavily doped body regions 112) the n-type dopants in substrate 100 tend to diffuse into epitaxial layer 102 thus forming the substrate out-diffusion region 101. Finally, dielectric caps 114 cover the filled trenches 109 and also partially cover source regions 110. Note that trench DMOS transistor 10 also typically includes one or more metal layers, which contact source regions 110, with adjacent metal layers separated by an insulating material. These metal layers are not shown in FIG. 1.
FIG. 2 shows a doping concentration profile, taken along a cross-section labeled “xx” in FIG. 1. Cross section xx is representative of the resistance path 116 that a drain-to-source current, IDS, encounters as charge carriers travel from source region 110 to the drain of trench DMOS transistor 10, when trench DMOS transistor is on. The various regions that comprise path 116 are source region 110, body region 108, portion 102a of epitaxial layer 102, substrate out-diffusion region 101 and substrate 100.
The resistance encountered by IDS due to the presence of these various regions is typically quantified as the drain-to-source resistance, RDS(on). A high RDS(on) limits certain performance characteristics of the transistor. For example, both the transconductance, gm, of the device, which is a measure of the current carrying capability of the device (given a certain gate voltage) and the frequency response of the device, which characterizes the speed of the device, are reduced for higher RDS(on). Another factor that limits the speed of the trench DMOS transistor is the gate oxide charge, Qg. The higher Qg is the larger the gate-to-drain overlap capacitance becomes and, consequently, the lower the switching capability of the device becomes.
Because the drain-source voltage is dropped almost entirely across the channel region, which comprises the body and epitaxial layers, the channel length, channel resistance and channel concentration profile are critical characteristics that affect the operating performance of a trench MOSFET. Whereas the absolute values of these characteristics are important, so too is the controllability of their variation. Wide device-to-device variations negatively affect the reproducibility of a device having desired performance capabilities.